Data processing systems are used in myriad applications which touch virtually every aspect of life. In applications where the data processing system uses battery power for any substantial length of time, it is particularly desirable to be able to minimize the power consumption of the data processing system. Examples of systems wherein battery power is used for substantial periods of time include portable data processing systems such as notebook and sub-notebook computer systems, and data processing systems which are employed in remote locations, hazardous weather areas, or earthquake prone areas. As discussed below, spurious transitions are an important factor in power consumption.
Due to finite propagation delays from one logic block of the data processing circuitry to the next logic block, critical races, or dynamic hazards, are inherent in static logic designs, whether full static, complementary pass-gate logic (CPL), or double pass-gate logic (DPL). These dynamic hazards can cause a logic node to have multiple transitions within a single clock cycle before settling to the correct logic level. This unnecessary switching activity is referred to as spurious transitions, and in some circuits it can consume over 30% more energy than is required to perform the data processing computation for which those circuits are designed. Although dynamic logic such as pre-charged domino exhibits only one transition per clock cycle, it can have a considerable overhead in power due to clock signal loading, clock drivers and additional gate capacitances.
FIG. 1 illustrates the sum output waveforms from a 0.6 micron CMOS, 100 MHz, 32-bit carry look-ahead adder (CLA) implemented in double pass-gate logic. The amplitude and width of the spurious transitions, such as 11, 13 and 15, vary depending on the sequence of input patterns. In some cases, many spurious transitions can occur before a valid one, as in the train of spurious transitions at 15. These spurious transitions impact not only power consumption, but clearly can also adversely affect the functional operation of the adder.
One way to remove spurious transitions in static logic is to equalize the delay of multiple circuit paths, but this requires the addition of delay elements which consume power and make this approach impractical.
It is therefore desirable to provide a technique which reduces spurious transitions and also eliminates more power consumption than it introduces.
The present invention provides a technique for reducing spurious transitions at desired logic nodes within data processing circuitry, and the technique reduces more power consumption than it introduces.